Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data (2023)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; TOLÊDO, RODRIGO DO NASCIMENTO - EP
- Unidade: EP
- DOI: 10.29292/jics.v18il.653
- Subjects: TRANSISTORES; CIRCUITOS ANALÓGICOS; NANOTECNOLOGIA
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher place: Porto Alegre
- Date published: 2023
- Source:
- Título do periódico: Journal of Integrated Circuits and Systems
- Volume/Número/Paginação/Ano: v.18, n.1, p. 1-6, 2023
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
TOLEDO, Rodrigo do Nascimento e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data. Journal of Integrated Circuits and Systems, v. 18, n. 1, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.29292/jics.v18i1.653. Acesso em: 02 jun. 2024. -
APA
Toledo, R. do N., Martino, J. A., & Agopian, P. G. D. (2023). Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data. Journal of Integrated Circuits and Systems, 18( 1), 1-6. doi:10.29292/jics.v18il.653 -
NLM
Toledo R do N, Martino JA, Agopian PGD. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data [Internet]. Journal of Integrated Circuits and Systems. 2023 ;18( 1): 1-6.[citado 2024 jun. 02 ] Available from: https://doi.org/10.29292/jics.v18i1.653 -
Vancouver
Toledo R do N, Martino JA, Agopian PGD. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data [Internet]. Journal of Integrated Circuits and Systems. 2023 ;18( 1): 1-6.[citado 2024 jun. 02 ] Available from: https://doi.org/10.29292/jics.v18i1.653 - Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies
- Nanowire TFET with different source compositions applied to low-dropout voltage regulator
- Regulador linear de baixa queda de tensão projetado com TFETs fabricados em nanofios de silício
- Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data
- The leakage drain current behavior in graded-channel SOI nMOSFETs operating up to 300 o.C
- Comparison between the leakage drain current behavior in SOI nMOSFETs and SOI nMOSFETs operating at 300 o. C
- Obtenção da estrutura de perfil de um transistor MOS a partir de parâmetros PSPICE
- Components of the leakage drain current in accumulation-mode SOI pMOSFETs at high temperatures
- A novel simple method to extract the effective LDD doping concentration on fully depleted SOI NMOSFET
- The graded-channel SOI NMOSFET and its potential to analog applications
Informações sobre o DOI: 10.29292/jics.v18il.653 (Fonte: oaDOI API)
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